The present invention relates to a semiconductor memory in a technology effectively applied, for example, to a bipolar-type random access memory (RAM) comprising emitter coupled logic (ECL) circuits or a bipolar complementary MOS (CMOS) RAM including bipolar transistors, p-channel MOSFETs, and n-channel MOSFETs.
There has been commonly used a bipolar RAM constituted with ECL circuits. The RAMs of the bipolar type are classified into two types including a so-called 10 K type with the source voltage set to -5.2 V and a so-called 100 K type with the source voltage set to -4.5 V.
The bipolar RAM has been described, for example, in the Japanese Patent Laid-Open No. 58-60487.
Input circuits and logic gate circuits constituting a peripheral circuit system of such RAM of the bipolar type includes as a basic configuration current switch circuit having a differential transistor. These logic gate circuits have logic threshold levels each set by a reference potential -Vbb supplied to a base of the differential transistor.
In order to establish the reference potential -Vbb, the RAM of the bipolar type includes a 10 K-type constant voltage generate circuit including a level generate circuit VG3 and an emitter follower output circuit V03 and a 100 K-type constant voltage generate circuit VG4 including a level generate circuit V04 and an emitter follower output circuit V04. These constant voltage generate circuits are alternatively set to be effective through a master slice operation depending on the power supply voltage supplied to the bipolar-type RAM. The contant voltage generate circuits VG3 and VG4 are respectively formed, for example, at the ends of a semiconductor substrate SUB as shown in FIG. 4 and one of the constant voltage generate circuits set to be effective supplies the reference voltage -Vbb to all circuits in the semiconductor substrate SUB. Consequently, since the reference potential -Vbb is supplied from the constant voltage generate circuit to the respective current switch circuits and the length of each lines used to supply the reference potential is increased, the reference potential -Vbb is accordingly decreased due to the wiring resistance of the lines and the like. As a result, the logical threshold levels of the input circuits and logic gate circuits are changed and hence the operation of the RAM of the bipolar type becomes unstable.
On the other hand, the reference potential -Vbb generated by the constant voltage generate circuit VG3 or VG4 is supplied to a plurality of current switch circuits, namely, the reference voltage -Vbb is supplied to bases of a relatively large number of transistors. Consequently, when the states of a plurality of current switch circuits vary at the same time, there appears a substantial change at the same time in each base current of the plural transistors to which the reference potential -Vbb is supplied. As a result, the reference potential -Vbb is changed. To prevent this adverse phenomenon, as shown in FIG. 7, there are added to the constant voltage generate circuit capacitors C5-C6 or C7-C8 each having a relatively large electrostatic capacity. This enables the variation in the reference level to be effectively suppressed. However, when this method is employed, for each of the two constant voltage generate circuits VG3 and VG4 integrated in the RAM of the bipolar type, the capacitors C5-C6 and C7-C8 each occupying a relatively large area are respectively required to be disposed. Consequently, the layout efficiency of the semiconductor substrate is reduced and the chip size is hence increased.